PAVANKUMAR MEDA
Singapore
Summary
- Working as ATE Test Development Engineer for Qualcomm Snapdragon Radio(RF) chips and contributed to more than 8 projects on 4G/5G technology.
- Lead role for Singapore team with collaborating US team to develop production testing solution for RF 5G Products on Teradyne Ultraflex Tester platform.
- Skilled on Test program development and Release to SATs for the production test,
- Yield and TT improvement methodologies for the Test cost savings.
- Expertise on Mixed-signal IP validation on ATE such as Sigma-Delta ADC, SAR ADC, DAC, ETDAC and mixed-signal PLL on RF chip for baseband portion to operate converters.
- Worked on Validation of High-speed protocol Qlink which is Qualcomm's own proprietary used for communication between RF and modem for 5G high-speed data transfer.
- Working experience on Teradyne Uflex(RF-Mixed signal) and V93K(Digital) tester platforms. Basic knowledge on Digital DFT concepts like ATPG, scan, BIST algorithms and IDDQ testing. Basic Understanding of Load board design and Verification and Programming language
- Understanding on C, C++, Visual Basics for Test.
- Knowledge on SVN and Github for the Test program code management across teams,
- Integration of Test program from different modules and release to production. Debugged Digital blocks like ATPG and MBIST using debugging tools like Pinmargin, shmoo tool and timing diagram on V93k platform.
Overview
11
11
years of professional experience
Work History
Staff ATE Test Development Engineer
Qualcomm Global Trading PTE ltd
10.2017 - Current
- RF Transceiver SOC validation on Teradyne Ultraflex (Uflex) Tester platform.
- Expertise on Mixed-signal IP validation such as ADC/DAC/PLL and High-speed protocol verification to support 18GBPS data transfer between RF SOC to modem.
- Representing the project Team from the Singapore site to collaborate with US team for project execution and NPI Test development.
- Test program releases to SATs for production testing for both wafer level and package level.
- Monitoring yield and test time improvement methodologies to maintain cost-effective test solutions.
Test Development Engineer for Burn In
Tessolve Semiconductor PTE ltd
02.2016 - 10.2017
- Automotive Chips at Infineon Technologies.
- Developed Test Program and production ramp-up support for burn-in insertion for Automotive chips on Burn in Oven with Test Instrument to run Dynamic Burn-In to sort out early life failures.
- High-density site testing on HW with On-chip BIST techniques using JTAG protocol for Controllability and observability.
ATE Test Engineer
Tessolve Semiconductor pvt Ltd
04.2013 - 01.2016
- Digital devices on V93K tester platform
- Worked on developing test solutions for Qualcomm MSM chips SCAN-based tests such as structural tests ATPG SAF, TDF, PDF, and Memory tests MBIST/LVMBIST Retention tests, IDDQ tests for leakage current on chip.
- Worked closely with DFT teams to isolate fails based on failing logs and memory diagnostic tests such as QMFAT to memory Test and repair.
Education
Bachelor of Technology - Electronics and Communications Engineering
Santhiram Engineering College, JNT University
Andhra Pradesh, India05.2012
Skills
- NPI Test development on Ultraflex and Advantest 93k
- C, Visual Basic and Python coding for automation and flow generation
- Knowledge on OOPs concepts
- Version control: SVN and GITHUB
- Knowledge on Mixed signal concepts
- Knowledge on DFT basics
- TTR and yield improvement efficiently
- Test cost improvement
- HW schematic and design for ATE Testing
Accomplishments
Achieved Test time reductions on Mixed signal by developing test methods to access on die IU processor for the data computations and Input/output access for a Test.
Able to achieve ~70% TT reductions by developing methods to use IU process inside RF SOC for testing with 'C' Language programming and compile into Chip readable registers using LLVM compilers.
This approach minimizes Instrument usage on production testing which directly impacting Test cost.
Tester Platforms
- Teradyne Ultra Flex, 10/2017, Present,
- RF Trans receiver Test development on ATE Ultra flex Teradyne using Visual Basic Programming. Mixed Signal Modules characterization on ATE for multiple Qualcomm SDR Trans receivers.
- ATE test program integration across all modules for RF Trans receiver and Test program release to SATs for production. Following test program release process through Agile for WS and FT test program releases to production and follow up with SATs for issues.
- Working experience on BBRX ADC/FBRX ADC (sigma delta) characterization such as Signal Power, Gain, SNDR, RSB, Noise measurements (ORN, IRN). GNSSADC (SAR type) characterization which is a part of GNSS subsystem in the Base band portion.
- ETDAC validation on ATE which is supplying the optimal voltages to RF power amplifier for Transmitter using Envelope tracking technique. Mixed signal PLL validation such as measuring Lock detect and PLL frequencies for LVDS.
- Worked on characterizing High speed interface char for Qlink latest generations which is used to communicate between RF transceiver and MDM Modem subsystem., SDR855 RF Trans receiver, SDR855 is the first multi-mode/multi-band RF transceiver using SECs 14LPC-RF process and will be packaged using flip chip technology.
- VERIGY 93K, 04/2013, 01/2016, Test Program development for wafer and Production program for Package level testing.
- Point of Contact and Interact with Design and DFT Engineers in on-site and off-shore to understand and resolve/debug device functional/characterization issues.
- Remote test debug with testers in San Diego, and Singapore (TCE) from Tessolve India Pvt Ltd and worked with SAT house for Test Program release., .
- IBIS(Intelligent Burn In System), 02/2016, 09/2017, Performing reliability checks on automotive chips to weed out the early failures. Working knowledge on stress tests HTOL, HTOL2, NVMBI and PRS. Test program releases for the production BI screen run on IBIS ovens. Closely working with the production team to resolve issues on verification. Performing different kind of stress test at elevated temperature, high voltage and dynamic operation for a predefined period of time to estimate the life time of the device.
Personal Information
Title: Staff ATE Test Development Engineer
Languages
Telugu
Bilingual or Proficient (C2)
English
Advanced (C1)
Timeline
Staff ATE Test Development Engineer
Qualcomm Global Trading PTE ltd
10.2017 - Current
Test Development Engineer for Burn In
Tessolve Semiconductor PTE ltd
02.2016 - 10.2017
ATE Test Engineer
Tessolve Semiconductor pvt Ltd
04.2013 - 01.2016
Bachelor of Technology - Electronics and Communications Engineering
Santhiram Engineering College, JNT University
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