Analog Design Engineer
Bitmain Development PTE. LTD.
04.2025 - Current
- Design SRAM IP at low supply voltage (0.525V or lower) and maximize its access frequency while maintaining low power consumption.
- While ensuring the yield requirement, maximize throughput and minimize the power consumption of SRAM IP. Ensure the accuracy of signal transmission.
- The SRAM IP is based on TSMC N4C (4nm) or a more advanced technology node. Responsible for completing some layout of certain blocks based on the floorplan provided by senior layout engineers.
- Collaborate with senior layout engineers to reduce the area of SRAM IP.
