Kautilya Phani
Hyderabad
Summary
- Innovative Senior Software Engineer with 5 years and 7 months of experience.
- Graduated from BITS Pilani in 2019 with an 81% CGPA.
- In-depth understanding of Object-Oriented Programming, data structures, and algorithms.
- Experience in handling multiple projects in a team setup, and driving home all deliverables on time.
- Mentored and trained juniors to bring them up to speed.
Overview
7
7
years of professional experience
Work History
Senior Software Engineer
AMD-Xilinx
Hyderabad
07.2023 - Current
- Developed an end-to-end Dynamic Function Exchange Database using Protobuf to manage and store comprehensive Partial Reconfiguration data.
- Development and ownership of the below C++ tools to streamline transitions between design implementations.
- Buffer insertion (insert LUTs to protect the design routing).
- Partial Reconfiguration Consistency Checker (to ensure the static region is intact across implementations).
- Visualization (Vivado GUI enablement)
- Netlist carver (carve netlist to enable the next implementation).
- Network-on-Chip (ID generation for NoC to enable their placement and routing).
- Unit test case creation to maintain tool robustness.
Software Engineer II
AMD-Xilinx
Hyderabad
07.2021 - 07.2023
- Served as the first resource in Hyderabad to master the device timing tool and subsequently trained and managed a team of 3
- Enhanced the timing tool with several checkers and robustness and emerged as the main point of contact.
- Further developed our timing tool into an end-to-end workflow to capture timing data on the device, which reduced TAT by 5x. This tool was extensively used all over the team.
- Enabled the team to meet multiple critical customer deadlines.
- Honored with 'Best Team Player' award across my division for coordinating with multiple teams and driving home all deliverables before time
- Won the Best Poster award in AMD for contributions to timing analysis using machine learning. This project is based on predicting the delay values and use them as input to our timing tool. This effort helped in providing timing data for device months in advance without having to wait for actual inputs to arrive
Software Engineer I
Xilinx
Hyderabad
07.2019 - 07.2021
- Developed a verification tool (linter) to ensure the accuracy of inputs received for the device timing flow
- Worked on capturing the software version of the device
- Cross-team collaboration across multiple time zones to meet tight deadlines
Intern
Intel
Bangalore
07.2018 - 01.2019
- Worked on Physical Design of System of Chip
Education
Bachelor of Science - Electrical & Electronics
Bits Pilani
Hyderabad, Telangana05.2019
Skills
- C
- Python
- Object Oriented Programming
- Operating Systems
- Linux
- DSA
- XML
- TCL
- JSON
- Design and development
- Virtualization
Timeline
Senior Software Engineer
AMD-Xilinx
07.2023 - Current
Software Engineer II
AMD-Xilinx
07.2021 - 07.2023
Software Engineer I
Xilinx
07.2019 - 07.2021
Intern
Intel
07.2018 - 01.2019
Bachelor of Science - Electrical & Electronics
Bits Pilani
Similar Profiles
SNEHITHA JADASNEHITHA JADA
Senior Software Development Engineer at AMD India Pvt Ltd (AMD-Xilinx)Senior Software Development Engineer at AMD India Pvt Ltd (AMD-Xilinx)
Yong Ling ChanYong Ling Chan
MTS Staff Engineer , Product Engineering at AMD-Xilinx Asia Pacific Pte. Ltd.MTS Staff Engineer , Product Engineering at AMD-Xilinx Asia Pacific Pte. Ltd.
Angela MirandaAngela Miranda
Network Operations Engineer at AMD / Xilinx Under OPUS IT Services Ltd.Network Operations Engineer at AMD / Xilinx Under OPUS IT Services Ltd.