Dance
Yufei Zhang
Assoc Staff Design Engineer
Summary
A seasoned Assoc Staff Design Engineer from Silicon Labs, I excel in leading secure element subsystem verification and silicon validation for IoT products. My expertise spans VLSI, UVM, and scripting in Python, complemented by a talent for mentoring new engineers. Achievements include pioneering a crypto verification model and enhancing chip connectivity through formal verification.
Overview
6
6
years of professional experience
6
6
years of post-secondary education
2
2
Languages
Work History
Assoc Staff Design Engineer
Silicon Labs
04.2024 - Current
- Lead Secure Element (SE) sub-system verification work for 40nm and 22nm IoT products
- Lead effort of security feature for multiple 40nm and 22nm chips silicon validation
- researched and built from scratch on crypto verification model (DPI-C) with UVM interaction
- intensively worked on chip/sub-system level functional simulation and gate-level simulation
- lead effort of multiple 40nm chips connectivity checks via formal methodology
- educate and guide new employees
Senior Design Engineer
Silicon Labs
05.2021 - 04.2024
- QSPI verification architect and initial test bench development
- Soft modem (co-processors) bench development and automation support
- Secure element (SE) / Virtual Secure Element (VSE) test development and sub-system bench architect
- formal verification (connection check, property check, auto check) of bus level security (BLS), GPIO, DMA matrix features
- Matlab fixed point modelling and simulation with UVM of demodulator filter chain
- chip verification lead on one of the latest 40nm project (2022), including test planning, test development, radio (short-range wireless) test and firmware setup, power and gate level simulation
- verification lead of new generation secure hardware platform, in charge of overall architecture spec review, test planning, UVM bench improvements, verilog bench setup, test code writing/execution, simulation firmware development, rtl design bug tracking and fixes.
- automation flow support (python) and security tool evaluation
- interns coaching
Design Engineer
Silicon Labs
08.2018 - 04.2021
- C based system level test development for multiple projects
- RTL (power aware) and Gate level simulation
- formal verification in terms of property check and connectivity check
- FPGA prototyping and test case development
- Silicon Validation (low level communication i.e. JLink, python automation, IAR debug IDE)
- UVM/SV based test bench development for IP blocks (glitchdetection) and Chip level environment
- Real Number Model development and simulation
- Verification Plan architecting
- python/tcl/bash/perl scripting for automation and project flow development
Education
Master of Engineering - Electronics Engineering
Nanyang Technological University
Singapore 08.2016 - 08.2018
Bachelor of Engineering - Electronic Engineering
Nanyang Technological University
Singapore 08.2012 - 06.2016
Skills
VLSI
VHDL
UVM
Formal Verification
Verilog/SystemVerilog
C programming
Scripting (tcl, perl, python)
Interests
Music (part-time DJ)
Hiking
Cooking
Timeline
Assoc Staff Design Engineer
Silicon Labs
04.2024 - Current
Senior Design Engineer
Silicon Labs
05.2021 - 04.2024
Design Engineer
Silicon Labs
08.2018 - 04.2021
Master of Engineering - Electronics Engineering
Nanyang Technological University
08.2016 - 08.2018
Bachelor of Engineering - Electronic Engineering
Nanyang Technological University
08.2012 - 06.2016
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