YEN LENG NG
Singapore
Summary
A detailed-oriented and having 6.9 years' experience in parametric test on wafer level in semiconductor field. In-depth knowledge in hands on the Agilent/Keysight tester & Tel prober for test issue debugging purpose. Worked as a Product Engineer role for product yield improvement. A dedicated team member to support and work as a team on daily operation issue or work-related information sharing. A flexible and dynamic person to accept on any new work arrangement and willing to accept new challenge to start up new project as assigned.
Overview
10
10
years of professional experience
Work History
Senior Product Engineer
Micron Semiconductor Asia Operations Pte Ltd.
06.2022 - Current
- Responsible for uMCP (UFS Multi-Chip Package) backend test flow development
- Responsible for build testing and NPI sample delivery
- Responsible for backed test step (DRAM BURN, HOT/COLD TEST) failure analysis and yield improvement
- Drive uMCP project overall backend yield and support project qualification milestone achievement
Senior Engineer ETEST/Backgrind (Parametric Test)
GLOBALFOUNDRIES Singapore Pte. Ltd.
07.2020 - 05.2022
- Develop new Electrical Parametric Test (E-Test) program & Algorithm for Test macros or testchips on new device
- Implement E-Test programs optimization for better electrical performances and faster throughput
- Perform E-Test program correlations and buyoff data for new test hardware
- Troubleshooting E-Test related issues (E-test program biasing, C algorithm, testing methodology, tools or probe card) and minimize equipment downtime
- Able to operate manual testing on Agilent/Keysight tester and prober for troubleshooting purpose
- Working closely with TD Process integration Teams and TD Device Teams to improve electrical parametric test data
- Maintain proper documentation of test specification and operating
- Design new ET probe cards configuration to meet customer electrical performance by working with Probe Card Vendor
- Working on Unix, Agilent/Keysight tester environment and TEL Prober
- Prepare E-test programs transfer to productions
- Attended JMP internal training for E-Test data analysis
- Able to use JMP to plot E-test data and prepare E-test data report
- Working on another new project development, which is to setup RF testing on wafer testchips level with Keysight PXIe (PCI extension for instruments) & Telprecio prober
- Deal with Keysight Vendor to integrate Keysight Tester, telprecio prober and PXIe instruments to perform RF automation testing on wafer level
- Self-study and setup STIL (Standard Test Interface Language) config file to produce I2C pattern to send command through the PXIe Digital Stimulus Response with PPMU to the testchip (the I2C pattern is provided by customer) and perform RF testing
Engineer 2 ETEST/Backgrind (Parametric Test)
GLOBALFOUNDRIES Singapore Pte. Ltd.
04.2018 - 06.2020
- Develop new Electrical Parametric Test (E-Test) program for Test macros or testchips on new device
- Implement E-Test programs optimization for better electrical performances and faster throughput
- Perform E-Test program correlations and buyoff data for new test hardware
- Troubleshooting E-Test related issues (E-test program biasing, C algorithm, testing methodology, tools or probe card) and minimize equipment downtime
- Able to operate manual testing on Agilent/Keysight tester and prober for troubleshooting purpose
- Working closely with TD Process integration Teams and TD Device Teams to improve electrical parametric test data
- Maintain proper documentation of test specification and operating
- Design new ET probe cards configuration to meet customer electrical performance by working with Probe Card Vendor
- Working on Unix, Agilent/Keysight tester environment and TEL Prober
- Prepare E-test programs transfer to productions
- Attended JMP internal training for E-Test data analysis
- Able to use JMP to plot E-test data and prepare E-test data report
- Working on another new project development, which is to setup RF testing on wafer testchips level with Keysight PXIe (PCI extension for instruments) & Telprecio prober
- Deal with Keysight Vendor to integrate Keysight Tester, telprecio prober and PXIe instruments to perform RF automation testing on wafer level
- Self-study and setup STIL (Standard Test Interface Language) config file to produce I2C pattern to send command through the PXIe Digital Stimulus Response with PPMU to the testchip (the I2C pattern is provided by customer) and perform RF testing
Engineer 1 ETEST/Backgrind (Parametric Test)
GLOBALFOUNDRIES Singapore Pte. Ltd.
06.2015 - 03.2018
- Develop new Electrical Parametric Test (E-Test) program for Test macros or testchips on new device
- Implement E-Test programs optimization for better electrical performances and faster throughput
- Perform E-Test program correlations and buyoff data for new test hardware
- Troubleshooting E-Test related issues (E-test program biasing, C algorithm, testing methodology, tools or probe card) and minimize equipment downtime
- Able to operate manual testing on Agilent/Keysight tester and prober for troubleshooting purpose
- Working closely with TD Process integration Teams and TD Device Teams to improve electrical parametric test data
- Maintain proper documentation of test specification and operating
Electrical Design Engineer
Jurong Shipyard Pte. Ltd.
08.2014 - 05.2015
- Handling Drilling System - electrical design in a Drillship
- Design electrical interconnection drawing of drilling system
- Comment Vendor's issued drawings of electrical and general arrangement of drilling system equipment for approval
- Using AVEVA software to design Interconnection drawing
- Using Auto cad for layout design and system termination drawing
Education
Bachelor of Engineering (Honours) - Electrical-Mechatronics
Universiti Teknologi Malaysia(UTM)
06.2014
Sijil Tinggi Pelajaran Malaysia (STPM) -
Sekolah Tinggi Muar (High School Muar)
01.2009
Skills
- Manual Testing
- Agilent/Keysight Tester
- Tel prober
- Keysight PXIe system
- C Programming
- Unix/Linux platform
Languages
English
Mandarin
Hobbies and Interests
- Playing Badminton
- Playing Chess
Personal Information
- Title: Test Engineer
- Date of Birth: 02/16/90
- Nationality: Malaysia Singapore PR
Timeline
Senior Product Engineer
Micron Semiconductor Asia Operations Pte Ltd.
06.2022 - Current
Senior Engineer ETEST/Backgrind (Parametric Test)
GLOBALFOUNDRIES Singapore Pte. Ltd.
07.2020 - 05.2022
Engineer 2 ETEST/Backgrind (Parametric Test)
GLOBALFOUNDRIES Singapore Pte. Ltd.
04.2018 - 06.2020
Engineer 1 ETEST/Backgrind (Parametric Test)
GLOBALFOUNDRIES Singapore Pte. Ltd.
06.2015 - 03.2018
Electrical Design Engineer
Jurong Shipyard Pte. Ltd.
08.2014 - 05.2015
Sijil Tinggi Pelajaran Malaysia (STPM) -
Sekolah Tinggi Muar (High School Muar)
Bachelor of Engineering (Honours) - Electrical-Mechatronics
Universiti Teknologi Malaysia(UTM)
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