Graduated Computer Engineering Technology of HCM City University of Technology and Education.
2 years of experience with Functional Verification.
Basic knowledge on verification language Verilog and System Verilog.
Basic knowledge with UVM verification methodology.
Experience with AXI, APB protocol.
Overview
2
2
years of professional experience
Work History
Verification Engineer
Renesas VietNam
07.2022 - Current
Working on developing ScoreBoard on uvm_en to verify for new function on IP module (UT view point).
Create a base sequence and a base UVM test based on MUVE standard (UT view point).
Handle checklist, create the new patterns, update UT environment and UT specification for UT environment (for both the IP module using UVM environment and using System C environment)(UT view point).
Create the verification plan, coverage plan, analyze and improve the coverage results (UT view point).
Debug and propose the bug fixings (UT view point).
Create the script Perl to auto judgement PASS/FAIL for the regression(UT view point).
Create the new patterns using the assembly language.
Understand the AXI, APB protocol
Education
Bachelor of Engineering Technology - Computer Engineering Technology
HCM CITY UNIVERSITY of TECHNOLOGY And EDUCATION
Ho Chi Minh City, Vietnam
07-2022
Skills
After 2 years working at Renesas Company, the first and second years I was appreciated level 4 for my performance
I got the toeic certification 780 at Aug242024
Timeline
Verification Engineer
Renesas VietNam
07.2022 - Current
Bachelor of Engineering Technology - Computer Engineering Technology
Major Education, English Centre – Ho Chi Minh City, Vietnam at Major English CentreMajor Education, English Centre – Ho Chi Minh City, Vietnam at Major English Centre