Summary
Overview
Work History
Education
Skills
Certification
Languages
Timeline
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VAISHNAVI BALAKRISHNAN

Summary

Process Integration and Yield Enhancement Engineer with 5+ years of semiconductor manufacturing experience at GlobalFoundries. Experienced in process integration, yield improvement, statistical process control (SPC), design of experiments (DOE), failure analysis, and high-volume manufacturing. Proven ability to drive root-cause investigations, optimize process windows, improve process capability, and collaborate with cross-functional engineering teams. Seeking Process Integration, Yield Enhancement, Product Integration, or Technology Development roles within advanced semiconductor manufacturing.

Overview

1
1
Certification
5
5
years of professional experience

Work History

Process Integration & Yield Enhancement Engineer

GLOBALFOUNDRIES PVT LTD
Singapore
07.2021 - 05.2026
  • Support process integration and yield enhancement activities for high-volume 40nm automotive, low-power, and commercial technologies.
  • Managed high-volume device production lots and resolved inline electrical issues, consistently meeting Fab On-Time Delivery (OTD) targets.
  • Monitor critical process and electrical parameters to maintain manufacturing stability and process capability (Cpk > 1.33).
  • Lead yield excursion investigations through correlation of electrical test data, wafer maps, CDSEM measurements, SPC monitoring, and failure analysis.
  • Partnered with cross-functional Lithography teams to evaluate, define, and validate the FEM process window, ensuring robust process margins.
  • Utilized JMP and CD-SEM metrology to isolate root causes of 40nm wafer edge failures, optimizing CG CD uniformity to eliminate edge roll-off and boost die yield.
  • Partnered closely with Failure Analysis (FA) lab engineers to provide exact physical coordinates for sub-micron TEM / EFA cuts ensuring to get desired results.
  • Authored and updated Manufacturing Execution System (MES) e-routes to rapidly deploy 40nm process optimization changes from module/ PI, accelerating the baseline yield learning curve.
  • Executed DOE studies using JMP to evaluate process windows and improve manufacturing robustness.
  • Performed OOC/OOS investigations and implemented corrective actions to improve process stability.
  • Raised PCRB and understood the requirement for PCRB opening and follow through with qual plan and analyze data using required software and CR closure.
  • Analyzed SPC charts using SPACE and investigated all issues related to yield improvement.
  • Ensured the BKM changes are tagged in Lots to improve troubleshooting.
  • Worked closely with lithography, implant, reliability, and manufacturing teams to resolve process-related yield issues
  • Developed technical documentation for engineering processes and procedures.
  • Facilitated root cause analysis sessions to resolve complex technical issues, improving reliability of production lines.
  • Developed and implemented process improvement initiatives, resulting in reduced cycle times and increased yield.
  • Led cross-functional teams to optimize semiconductor fabrication processes, enhancing operational efficiency.

Education

Master of Science - Electronics

Nanyang Technological University
Singapore
06-2021

Bachelor of Engineering - Electronics and Communication Engineering

Anna University, K.S.Rangasamy College of Engineering
India
04-2017

Skills

  • Process improvement
  • Yield enhancement
  • Statistical process control
  • JMP proficiency
  • Root-cause analysis
  • Failure analysis

Certification

  • Yellow Belt in Lean six sigma.
  • Improved wafer-edge 1% yield through lithography CD optimization.
  • Maintained process capability above manufacturing targets.
  • Successfully supported multiple process optimization projects from evaluation through production deployment.

Languages

Fluent in English, Hindi and Tamil

Timeline

Process Integration & Yield Enhancement Engineer

GLOBALFOUNDRIES PVT LTD
07.2021 - 05.2026

Bachelor of Engineering - Electronics and Communication Engineering

Anna University, K.S.Rangasamy College of Engineering

Master of Science - Electronics

Nanyang Technological University
VAISHNAVI BALAKRISHNAN