Tang Yeap Hon
Ipoh
Summary
Dedicated and skilled Layout Design Engineer with 6 years of experience in the industry. Recognized for outstanding performance. Committed to delivering exceptional quality and service. Passionate about work and dedicated to contributing expertise to project success.
Overview
7
7
years of professional experience
Work History
Integrated Design Engineer ( Contractor )
MediaTek Singapore Pte Ltd
05.2024 - Current
- Involved 2 projects in 2nm process.
- Designed layout for local IO, local control, wldrv and completion cell to abut IO and control.
- Worked in all level of hierarchy from pmos/nmos cells to top IP level assembly using custom compiler.
- Work on ECO, clean up LVS/DRC in all compilers and also RV fixes and signal/power improvement, verify all compilers are pdv flow clean at top IP level.
- Ensured delivery of project milestones for complex layout development.
- Managed multiple projects simultaneously while adhering to strict deadlines and maintaining a high level of attention to detail.
Layout Design Engineer
Intel Microelectronic (M) Sdn. Bhd.
01.2020 - 04.2024
- Involved 3 compilers in 10nm process and 2 compilers in 5nm process.
- Designed layout for power generator, latch, select, address bus and level shifter subblock inside IO.
- Designed layout for power generator, code timer and level shifter subblock inside timer.
- Worked in all level of hierarchy from standard cells layout to top IP level assembly using virtuoso/clisoft.
- Work on ECO, clean up LVS/DRC in those compilers and also RV fixes and signal/power improvement, verify all compilers are pdv flow clean at top IP level.
- Ensured delivery of project milestones for complex layout development.
Intel Contract Employee
Intel Microelectronic (M) Sdn. Bhd.
11.2018 - 01.2020
- Learnt some layout drawing by using Genesys tool and understanding the structure of layout.
- Applied skill and knowledges in how to design the layout and routing all the signals by referring the schematic diagram.
- Learnt some skill on how to fix the design rule violations in the layout like trclvs and drcd.
Internship
Intel Microelectronic (M) Sdn. Bhd.
02.2018 - 07.2018
- Learnt some schematic diagram of the test program and understanding the process flow of the transceiver team’s test.
- Applied skill and knowledges in writing the automation script of data collection.
- Learnt some skill on debug the problem occurs on the test program.
- Learnt how to collect data from the machine.
Education
Bachelor of Science - Bachelor’s Degree in Electronics Engineering Technology (Electronic Industrial)
Universiti Teknikal Malaysia Melaka
2018
Skills
- Fast learner
- Technical skills
- Microsoft Excel, Word and Power Point
- Tools : AutoCAD, Multisim, CX-programmer, PIC C COMPILER, Proteus, Arduino IDE, FluidSIM, LabVIEW, genesys, virtuoso, clisoft, Custom Compiler
- C/C programming
Languages
Chinese (Mandarin)
Proficient
C2
English
Intermediate
B1
Malay
Upper Intermediate
B2
Japanese
Beginner
A1
Chinese (Cantonese)
Proficient
C2
Chinese (Mandarin)
Bilingual or Proficient (C2)
Timeline
Integrated Design Engineer ( Contractor )
MediaTek Singapore Pte Ltd
05.2024 - Current
Layout Design Engineer
Intel Microelectronic (M) Sdn. Bhd.
01.2020 - 04.2024
Intel Contract Employee
Intel Microelectronic (M) Sdn. Bhd.
11.2018 - 01.2020
Internship
Intel Microelectronic (M) Sdn. Bhd.
02.2018 - 07.2018
Bachelor of Science - Bachelor’s Degree in Electronics Engineering Technology (Electronic Industrial)
Universiti Teknikal Malaysia Melaka
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