TAN YI EN
SoC Physical Design Engineer
Summary
Accomplished SoC Physical Design Engineer from Mediatek Singapore, adept in advanced node technology (6nm to 3nm) and proficient in Innovus and Fusion Compiler. Equipped with strong problem-solving abilities, willingness to learn, and excellent communication skills. Poised to contribute to team success and achieve positive results. Ready to tackle new challenges.
Overview
3
3
years of professional experience
4
4
years of post-secondary education
Work History
SoC Physical Design Engineer
Mediatek Singapore Pte. Ltd.
10.2022 - Current
- Block owner in SoC Physical Design Projects at advanced technology nodes (6nm, 4nm, and 3nm).
- Experienced implementation of 5 macros simultaneously using Fusion Compiler.
- Experienced implementation on block with 2-3M instances, floorplan with multi-power domain design, and critical congestions by using Innovus.
- Execute methodologies including floorplanning, place and route, static timing analysis (STA), and engineer change order (ECO) stages.
- During the ECO stage, clean up Design Rule Violations (DRV), Physical Verification (PV), Electrical Rule Check (ERC), and Layout Versus Schematic (LVS).
Internship in Atom PG C&D and FPGA Department
INTEL MICROELECTRONICS (M) SDN BHD
07.2021 - 10.2021
- Completed MoHE Elite Internship Program (Front End Training, Fusion Compiler Training, Manufacturing & Product Engineering (MPE) Training, Synopsys Training, FPGA Training).
- Done 'SQLite3 to MSSQL Conversion' project to migrate all the data in the existing database to MSSQL server.
Education
Bachelor of Engineering (Electrical-Electronics) -
Universiti Teknologi Malaysia
09.2018 - 08.2022
Skills
Languages: English, Mandarin and Malay
Software: Innovus, Fusion Compiler, Tweaker
Programming Language: TCL, Python, C/C, Verilog, MATLAB
Technical Skills: Floorplanning Expertise, Placement Optimization, Routing Technologies, Static Timing Analysis, Physical Verification, Layout Versus Schematic
Timeline
SoC Physical Design Engineer
Mediatek Singapore Pte. Ltd.
10.2022 - Current
Internship in Atom PG C&D and FPGA Department
INTEL MICROELECTRONICS (M) SDN BHD
07.2021 - 10.2021
Bachelor of Engineering (Electrical-Electronics) -
Universiti Teknologi Malaysia
09.2018 - 08.2022
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