Summary
Overview
Work History
Education
Certification
Timeline
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Priyabrata Mishra

Senior Verification Engineer
Bengalaru

Summary

Dynamic Senior Verification Engineer with a robust background in ARM instruction set architecture, specializing in the development of advanced CPU verification tools. Expertise in creating comprehensive stress testing tools, enhancing system infrastructure, and automating power measurement architecture through Python programming. Proven track record as a Senior Lead Engineer at Qualcomm India, playing pivotal roles in CPU validation, including power, performance, and functional assessments of ARM-based Qualcomm SoCs. Committed to fostering innovation in CPU architecture while optimizing power and performance metrics for next-generation technology solutions.

Overview

5
5
years of professional experience
2
2
Certifications

Work History

Senior Verification Engineer

ARM Embedded Technologies
04.2025 - Current
  • Developing the RIS (Random Instruction Sequence) tool for the latest ARM cores.
  • Analyzing the coverage missing, and added features like the post-index variant of LS multistructure Neon instruction.
  • Developing the user's request KPI stats for various stats, including page crossing, etc.
  • Supporting users ( DV POC) for required config, power related feature enablement and debug.


Senior Lead Engineer

Qualcomm India
05.2022 - 04.2025
  • Leading comprehensive validation phases for the latest ARM-based CPUs across silicon stages.
  • Created comprehensive test cases for functional and performance validation for features like PAUTH, MPMM, and SVE ARM extensions.
  • Created diverse stress-testing tools to validate CPU pipelines, such as LSU and AGU intensive.
  • Developed a Python-based tool for execution using T32 and plotting (cx vs. mx), (mx vs. freq), and (cx vs. freq) smhoo plots across different DVFS points.
  • Perform static and dynamic power measurement across TT, FF, and SS parts, along with IDDQ current measurement using Kratos, and correlate with design estimates.
  • Developed a frequency checker bare-metal test case on the basis of the PMU cycle counter and generic timer as a sanity checker before performance activity.
  • Ported tinymembench and added various workloads, like QB, SHA, custom LSU stress, BTB stress, and Geekbench workloads, to measure the performance cycle, along with bandwidth, latency, and Dhrystone numbers.
  • Enhanced Kernel’s compatibility and performance for the Cortex-M target by executing multiple application-based tests in order to enrich the randomness.
  • Developed a DV multi-threaded kernel and verified the FSDB simulation with tarmac output.
  • Developed the system infrastructure using TF-A to execute 2 billion random instructions per day of RIT ELF’s back-to-back on silicon, as well as emulation platforms.
  • Developed the Sival Linux kernel stack to expose device interfaces to Linux applications using syscalls and custom libraries.
  • Automated power measurement architecture creation and Python-based infrastructure design by integrating next-gen UDAS with T32 and providing a second loop feedback mechanism to maintain the temperature across the back-to-back run by calibrating the TCU.

Senior Engineer

KPIT TECHNOLOGY
08.2020 - 04.2022
  • SOC prototype design with QEMU.
  • Design of SJA1000 (Philips) CAN controller using SystemC and integrated over ARM FVP Cortex M4 (error modules not implemented).
  • Co-simulation platform design with an integrated environment for multi-ECU simulation (from POC to initial production level).
  • Providing an approach to connect the UML model to the vehicle network (VEOS) through the CAN frame for HMI events generated at the infotainment cluster.
  • Converting a UML model to code-based virtual ECU for vehicle-level validation and inclusion in the vehicle-level regression testing platform using C++.
  • Driving initiatives regarding the new, upcoming middleware virtualization development.

Education

Master of Science - Embedded/VLSI design

Dhirubhai Ambani Institute of Information And Communication Technology
India
04.2001 -

Certification

Hacker Rank Problem solving certified (https://www.hackerrank.com/certificates/4d587bca1d95)

Timeline

Senior Verification Engineer

ARM Embedded Technologies
04.2025 - Current

Senior Lead Engineer

Qualcomm India
05.2022 - 04.2025

Senior Engineer

KPIT TECHNOLOGY
08.2020 - 04.2022

Master of Science - Embedded/VLSI design

Dhirubhai Ambani Institute of Information And Communication Technology
04.2001 -

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Priyabrata MishraSenior Verification Engineer