Maurizio CASTORINA

Job Responsibility:

Lead a group of 24 R&D process and process integration engineer in Singapore.

-Responsible to Develop new technology in the field of Power electronics : Si and WBG, starting from Proof of Concept to the Full release in production.

-Responsible as a Team leader of all the transfer in and out of Singapore for power discrete ( LV Pmos, HV Pmos, IGBT, SiC discrete (Pmos and Diodes).

-Support as technical reference any Technology transfer and development in foundry in Asia ( China , Korea etc), ensuring that the technical info needed for the success of the project are available for the involved team. I also participate to all the high importance technical discussion.

-Responsible for ADG of the collaborations with Singapore main University institute ( NTU, NUS, SIT) and reaserc institute ( IME , A*Star)

- Responsible of evaluation of new Tolls and new materials to create new enabling block to achieve technology better performance.

Achievements:

Technology Transfers in Singapore

OFT 100V F7 series

OFT 80V F7 Series

IGBT Emitter implant SW series

IGBT Emitter Implant LA

LV Pmos EHD7

SiC Diodes Gen 2++

SiC Diodes Blanck

Sic Diodes Gen 5

SiC Pmos Gen2

SiC Pmos Gen 3

Technology Transfer in foundry

IGBT Emitter implant in Samsung Korea

OFT 100V F7 series in HHGrace

Technology Developments

OFT 100V F8 Series

HBIP40V bipolar IC's

HBIP40V ESD protection

ULVF2 100V trench Shottkly Diode

On Going Projects

IGBT VHV (1350V to 1600V)

RCIGBT HI

RCIGBT LEIA MC

OFT 100V LL F8 series

OFT 80V F8 series

F8+ reliability improvement passivation scheme

F10 150V

ULVF2 120V

EBIP1 ESD protection

ETVB1 ESD protection

SiC Pmos Gen3 -Gen 4 8" Transfer in Singapore

Responsible of the Device engineer for new Technology in Catania Pilot line

Collaborating with Designer and Technology development Team to set up the new Technology Node.

Support the Transfer in mass production in the main manufacturing FAB in Catania

Lead a team of 12 Device engineers.

Lead a team of Parametric Test Engineer for Testing programs creation and maintenance (4 Engineer)

Responsible of Parametric Test production area in Catania 6" FAB (8 Operators + 2 Shift engineers)

Responsible of the Transfer from Pilot Line to 6" production of High Speed Bipolar Transistor.

After successfully qualified support as Device engineer the Technology in full production.

Number of collaborators 3 device engineer

Support the development of new LV Pmos technology node in collaboration with Design Team.

Flow chart creation

DOE

Electrical data analysis

Failure analysis

Technology developed

Ultra High density 3rd Gen 30V

Ultra High Density 3rd Gen 60V

Extreme high density 2nd gen 60V

Extreme High Density 3rd gen 60V

Extreme High Density 5th Gen 60 V