Indu Amit
Staff Engineer
Singapore
Summary
- 20+ years of experience in ASIC / SOC design, development and verification.
- Involved in all stages of hardware development from requirements analysis, design to development, testing and documentation of all phases.
- Experience in SoC/IP digital design and verification. Work closely with architecture and RTL designers to develop comprehensive verification plan based on SOC/IP specifications.
- Develop and execute the verification test plan by defining test strategy and test cases for manual and automated testing based on functional verification environment.
- Develop advanced verification environment and test bench components in System Verilog and UVM methodology. Build testbench components such as monitors, sequencers, sequences required to verify a DUT.
- Perform RTL and GATE level simulations, synthesis and timing closure.
- Perform coverage analysis on the SOC which involves code/assertion/toggle coverage using formal methodologies.
- Worked on SOC verification for MCU, top level digital IP blocks, peripherals like PCIe, spi, i2c, memories,DAP,JTAG, CPU sub-systems like DMA,IR
- Working experience on AMBA and bus protocols.
- Conduct non-regression for the chip and write/update scripts to automate the process. Jenkins and vmanager have been used for this.
- Very familiar with data base management methods like GIT / Clearcase. Able to do top level integrations to include the latest Tags in the verification environment and do sanity tests to check it does not break the flow.
Overview
21
21
years of professional experience
5
5
years of post-secondary education
3
3
Certifications
1
1
Language
Work History
Staff Engineer
Infineon Technologies
09.2022 - Current
- Lead the SOC Verification for a team responsible for CPU/PPU/DMA/IR/DAP/JTAG/virtualization/memories.
- Worked on verification of peripheral interfaces used for Audio and Sensors,communication protocols like i2c,spi,pcie
- Prepare the verification plan for a AMBA based product to verify the blocks,interfaces,busses,IO. This involves defining the test environment needed using the in-house iVC or mVC, 3rd part UVC and integrating all blocks to generate a testbench using UVM/SV to verify the DUT.
- Develop test patterns using UVM patterns and sequences.
- Developed a test model for DMA module using Perspec and ported already existing C++ test patterns of legacy products to Perspec patterns.
- Develop/modify/execute the verification test plan. This involves defining the functional points, identifying the way the test will be implemented, corner cases to be run, mapping the pattern after it is implemented and checking the results in non-regression using Jenkins.
- Perform RTL and GATE level simulations,timing closure.
- Perform coverage analysis and close the coverage gaps using formal verification, assertions and certitude analysis.
- Verify IP's using C/C++,SV for legacy products.
- Create/TRACK the JIRA's for the bugs.
Staff Engineer
ST Microelectronics
07.2014 - 09.2022
- Work closely with Architects and RTL designers to understand product specifications and participate in design reviews.
- Develop/modify/execute the verification test plan. This involves defining the functional points, identifying the way the test will be implemented, corner cases to be run, spec annotation, mapping the pattern after it is implemented and checking the results in non-regression.
- Develop advanced verification environment and test bench components in System Verilog / C UVM methodology.
- Perform RTL and GATE level simulations, synthesis and timing closure.
- Perform coverage analysis on the SOC which involves code/assertion/toggle coverage.
- Worked on multiple top level groups like for clocks/reset/power groups, top level digital IP integration groups, communication protocols or memories. I need to use tools like Jasper gold / pespec for verification.
- Manage non-regressions at SOC level.
Senior Engineer
Qualcomm
08.2011 - 12.2013
- Company Overview: Bangalore, India
- SoC/IP digital logic design and verification. This involved the RTL logic design, verification, GLS simulations, carrying out sanity checks and timing closure.
- Defining the Bus Interconnect architecture for chips and then designing the NoC (Network On Chip).
System Design Engineer
Solomon Systech Pte ltd
08.2008 - 10.2009
- Company Overview: Singapore
- The task involved Behavioral and RTL coding, Behavioral and gate level logic simulation, Logic synthesis and verification for modules/sub modules for Audio Codec Controller, GPIO and DMAC.
Senior Engineer
Honeywell Technology Solutions
02.2004 - 03.2008
- Company Overview: Bangalore, India
- Behavioral and RTL coding, Behavioral and gate level logic simulation, Logic synthesis, test bench development, testing analysis of code and net-list level and Static Timing Analysis.
- Worked on FPGA programming and verification.
Education
Bachelor of Engineering - Electronics & Communication
Maharshi Dayanand University
06.1999 - 05.2003
Post Graduate Diploma - SYSTEM PROGRAMMING & VLSI DESIGN
CENTRE FOR DEVELOPMENT OF ADVANCED COMPUTING
04.2003 - 01.2004
Skills
Test Plan definition and review
RTL/Gate/Mixed Signal simulations, synthesis, timing closure, coverage analysis, certitude analysis
Testbench Development using UVM
Formal Verification
Languages: C/C,System Verilog, UVM,Perspec, Perl/python scripting
Databases: GIT, Clearcase
Tools: Xcelium, Questasim, Jasper Gold, Jenkins
Certification
UVM Training from Cadence
Job Title
Staff Engineer
Timeline
Staff Engineer
Infineon Technologies
09.2022 - Current
Staff Engineer
ST Microelectronics
07.2014 - 09.2022
Senior Engineer
Qualcomm
08.2011 - 12.2013
System Design Engineer
Solomon Systech Pte ltd
08.2008 - 10.2009
Senior Engineer
Honeywell Technology Solutions
02.2004 - 03.2008
Post Graduate Diploma - SYSTEM PROGRAMMING & VLSI DESIGN
CENTRE FOR DEVELOPMENT OF ADVANCED COMPUTING
04.2003 - 01.2004
Bachelor of Engineering - Electronics & Communication
Maharshi Dayanand University
06.1999 - 05.2003
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