Agxin Justin Xavier
Singapore
Summary
Hardware Design Engineer with more than 11+ years of experience in Hardware design and development Seeking a challenging lead role in product design that requires engineering education and experience to design and develop innovative hardware solutions.
Overview
12
12
years of professional experience
Work History
Senior Hardware Design Engineer
Rapsodo pte ltd
04.2022 - Current
- Defining Hardware Requirements specification for Camera modules ,processing and computing's modules and 24Ghz Radar Modules.
- Block diagram and system architecture of the hardware ,Product Budget, Resource planing,Project Timeline ,Defining Mile stones and deliverables.
- Core components selection,Schematic design with Altium or Pads ,Design detailing ,Symbol and foot print creation of parts , Design documentation ,Power Budgeting ,De-rating ,AC DC analysis ,Power Architecture design Rough Placement , Thermal analysis and Simulation review ,ERC checks and Design reviews.
- PCB design ,Layer and route Planning,Power plane creation ,Stackup planing ,Setting constraints Routing ,length matching,Cleanup ,DRC Clearance Gerber generation assembly and fabrication documentation ,
- Coordination with Partners Vendors for SI and Simulation,Mechanical design,FAB and Assembly of PCB
- Test plan creation ,Defining software requirement ,Hardware bring up ,DVT,Functional Testing ,Product level testing ,Stress testing and margin testing ,Bug fixing ,Product certification,Specification and User guides for testing and manufacturing teams .
- Proto to pilot and mass production preparation ,Bug Fix testing,coordination with FAB and assembly house
- Resource management and collaboration with Firmware ,middleware software mechanical teams,business development,purchase,manufacturing and logistics teams
Hardware Engineer V Specialist
HPE ARUBA
11.2018 - 04.2022
- NPI /Pilot run board bring‑up, Testing co‑ordination, Support JDM/OEM in production planning
- Memory Qualification (Discrete and Modules‑ Volatile /Non‑Volatile ), FPGA's Qualification
- MSQ during AOS/PCN for active and passive discrete, DC‑DC, LDO, Clock solution's
- Replacement Identification for EOL Parts, Qualification of New parts, Design changes and approvals
- Code warrior DDR Validation, SI analysis, DVT ‑ SI Measurements and Timing Validation
- Climatic testing, Voltage /Temperature ‑Margin testing, Failure Analysis
- Debugging of Network Switches and Addressing quality and Production Automation issues
Tech Lead -Hardware Design
VVDN Technologies, Chennai
06.2016 - 11.2018
- Project Planning, Resource Management, Team building, ERP sign off
- PRD and HDD and Block level architecture design and review, Component selection
- Schematics design/drafting and review, AC/DC analysis, Power budget estimation,
- BOM optimization,class‑A BOM preparation and Project Budgeting
- PCB Design guideline preparation, Defining Impedance and length matching requirements
- Stack up planning, Defining power plane requirements, PCB design validation, SI/PI
- validation
- Gerber review and DFM /DFA checks, Mechanical design review
- Heat‑sink /Fan selection and Thermal design review, Wiring Diagrams review ,Addressing FAB query
- Software Input Documentation, Test Plan preparation, DVT and PCR document preparation
- Board bring‑up, Testing and Debugging, System Integration
- Production test setup development and documentation, Assembly Instruction preparation,
- Product certification for PTCRB, FCC and CISPR testing, Automotive transient testing
Hardware Design Engineer
Tata Power SED ,Banglore
05.2015 - 05.2016
- HRS and DR Documentation, Schematics design, Design Analysis, Power Budgeting
- ERP database management, Symbol and Footprint review for components
- PCB review, DDR3 interface validation, SI analysis for High‑speed serial links, PI analysis.
- Gerber review and DFM Checks, Mechanical Design review, Thermal Design review
- Stack‑up and Fabrication Input preparation and FAB house co‑ordination
- Board Bring‑up and testing, DDR3 NAND/NOR Flash interface Bring up testing
- RCW Creation, PTP and PTR documentation, Cabling design, Test Jig design
- Software Bring up support and system integration
- EIM/EMC Testing for the product in MIL‑STD461‑F for CE102/CE101,RE101,RE102
Hardware Engineer SI PCB Design
Data patterns, Chennai
07.2012 - 03.2015
- Symbol and Footprint creation, Validation of component library with datasheets
- ERP Database Management, Library Management
- Schematics design from Block diagrams and Architecture level inputs, Netlists Review
- PCB Design of Analog and Digital and RF boards in Standard and customized dimensions
- SI analysis for High‑speed serial links Pre and Post Layout Validation
- Stack‑up design and Fabrication Input preparation
- DDR3 interface validation, PI analysis, Constrain Definition
- PCB design review, Mechanical interference check, Constrain Validation
- Gerber documentation review and DFM/DFA Checks,
- Board Bring‑up and testing PTP and PTR documentation
Education
Bachelors - Electronics And Communications Engineering
St Xavier's Catholic College of Engineering
India04-2012
High School Diploma -
Yettacode Higher Secondary School
India03-2008
Skills
- Project Planning, Resource Management, Team building
- Schematics design using Dx‑designer or Schematic Capture, Altium designer pads
- Pre and Post Layout Simulation /analysis using Hyperlynx
- PCB design and review using Expedition PCB and OrCad PCB Designer Altium Designer and Pads
- EYE Diagrams for Serial links, IBIS‑AMI channel analysis for BER using scopes and simulation tools
- Timing analysis, Jitter and Skew analysis, DDR simulation
- Circuit simulations using LT SPICE and TINA
- BOM and Product documentation using MS OFFICE
- Component creation, Symbol and footprint validation using Library Manager
- DFM/ Analysis using ODB Viewer and Valor, Hyper‑lynx DRC
- Experience in using high‑speed DSO and MSO, SSA, Frequency counters for DVT and debugging
- Experience in Flashing and debugging tools like Code‑warrior, and CCS, Arduino, Keil, Dediprog
- Experience in using I2C and SPI protocol analyzers DDR detective PCI‑E express analyzers ,Salea
- ERP /Project Management using Team‑viewer Biz‑box and JIRA,confluence
- EMI/EMC certification clearance testing and debugging in MIL 461 E FCC 15 B and CISPR 22
Design Exposure
- Interface: I2C, I2S ,SPI, CAN,UART,RS 232,RS 485,USBC,3.0
- Analog Amplifiers and filters ,FMCW Radars MTR and LTR 24Ghz
- Memory:DDR3/4 (Discrete /DIMM),EMMC,uSD,NAND/NOR,M.2 SSD, SATA modules
- High‑speed Interfaces SGMII/RGMII, HDMI,DVI, LVDS PCIe 2.0 /3.0,MIPI‑CSI
- USB2.0, USB3.0 Ethernet 1G and 10 G
- Smart rate modules POE controller designs based on LTC modules
- Processor‑based, Controller‑based, FPGA based COM‑E or SOM based designs
- FMC based XMC based modules, VPX based signal processing module
- CMOS Image sensor IMX Sony OV/OG omnivision /Image signal Processor
- LTE /Wi‑Fi /BT modules
- TX1 ,NX,P2020,P2040,T2080, RK3588,RV1126 CPU designs
- Buck converters, LDO, POL regulators, BRICKS USBC ,Battery charge controller
Languages
Tamil
First Language
English
Proficient (C2)
C2
Websites
Timeline
Senior Hardware Design Engineer
Rapsodo pte ltd
04.2022 - Current
Hardware Engineer V Specialist
HPE ARUBA
11.2018 - 04.2022
Tech Lead -Hardware Design
VVDN Technologies, Chennai
06.2016 - 11.2018
Hardware Design Engineer
Tata Power SED ,Banglore
05.2015 - 05.2016
Hardware Engineer SI PCB Design
Data patterns, Chennai
07.2012 - 03.2015
Bachelors - Electronics And Communications Engineering
St Xavier's Catholic College of Engineering
High School Diploma -
Yettacode Higher Secondary School
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