Adithi Raghuraman
Summary
A Master's graduate in Integrated Circuits Design with 3+ years of experience, seeking an IC design role to contribute and grow in the semiconductor industry. A versatile and success-driven engineer, I thrive under pressure, value teamwork, and continuously seek learning opportunities to enhance my skills in ASIC design.
Overview
5
5
years of professional experience
Work History
Senior Design Engineer
MARVELL SEMICONDUCTORS ASIA PTE LTD
05.2022 - Current
- Develop timing constraints (SDC) , Setup synthesis flow
- Check clock paths in the design with Verdi and read FSDB to check dividers
- Perform Synthesis with synopsys design compiler to meet timing , area , performance
- Verify synthesis netlist with formality and conformal LEC tools
- Verify SDC correctness with GCA tools and conduct SDC review with design team
- Able to debug LEC issues and collaborate with design Team / DFT team
- Collaborate with DFT team for scan insertion and scan mode timing checks
- Run STA to check timing, Develop CTS SDC for PNR team
- Perform ECO to fix timing, max-transition and max-capacitance violations using DMSA tool
- Develop TCL/Perl scripts to automate netlist quality checks
- Perform power recovery on the netlist
- Generate TWF to check IR analysis and perform IR aware STA
- Resolving cross-talk and double switching violations throughout the design
DIGITAL DESIGN INTERN
MARVELL SEMICONDUCTORS ASIA PTE LTD
07.2021 - 05.2022
- Worked with RTL Low power optimization algorithms and Synthesis techniques
- Implementation of Clock Gating, Multibit flip flop, Multi corner multi-mode analysis
- Timing analysis post synthesis
- Worked with timing closure of different protocols such as SPI, SSPI, RGMII
GRADUATE RESEARCH ASSISTANT
NANYANG TECHNOLOGICAL UNIVERSITY
12.2020 - 06.2021
- Proficiency with RTL coding, Logic synthesis, timing constraints. Design of state machines, data paths and Contribute to Power Reduction, Timing Convergence.
- Perform RTL Coding and Synthesis for the Deep neural network object detectors
- Work with Verification and Physical Design engineers to deliver high-quality, high-performance, and power efficient designs
- Contributed to professionally-written scientific paper for publication.
Associate Software Engineer
BOSCH ENGINEERING AND BUSINESS SOLUTIONS
08.2019 - 08.2020
- Mainly involved in the Software development and testing of the Diesel Exhaust Gas System for Particulate Matter Sensor
- Knowledge about Automotive guidelines : AUTOSAR, ASIL
Education
Master of Science - Integrated Circuit Design
Nanyang Technological University
Singapore07-2022
Bachelor of Science - Electronics And Communication Engineering
Amrita School of Engineering
Bangalore06-2019
Skills
- SDC Development
- LEC Debugging
- GCA SDC checker
- TCL/Perl scripting
- Familiar with synopsys Verdi
- Proficient in synthesis, clock tree synthesis, static timing analysis
- Timing, Power ECO
- Sign-off timing closure with Prime-Time
Accomplishments
- Published "Scalable Hardware Acceleration of Non-Maximum Suppression" in 2021 International Conference on Computer-Aided Design (ICCAD).
- Published "NMOS-Only Schmitt Trigger-Based SRAM Cell" in 3rd International Conference on Electronics, Communication, and Aerospace Technology (ICECA 2019).
Timeline
Senior Design Engineer
MARVELL SEMICONDUCTORS ASIA PTE LTD
05.2022 - Current
DIGITAL DESIGN INTERN
MARVELL SEMICONDUCTORS ASIA PTE LTD
07.2021 - 05.2022
GRADUATE RESEARCH ASSISTANT
NANYANG TECHNOLOGICAL UNIVERSITY
12.2020 - 06.2021
Associate Software Engineer
BOSCH ENGINEERING AND BUSINESS SOLUTIONS
08.2019 - 08.2020
Master of Science - Integrated Circuit Design
Nanyang Technological University
Bachelor of Science - Electronics And Communication Engineering
Amrita School of Engineering
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