AARUSHE MAHAJAN
Singapore
Summary
As a seasoned professional in Physical Verification, I understand chip verification at both SoC and block levels. I am eager to apply my current expertise to a dynamic new role, where I can further expand my knowledge and skill set. My goal is to contribute meaningfully to the team while continuing to learn and grow within the position. My commitment to excellence and drive for continuous improvement make me an ideal candidate to bring value and efficiency to your organization.
Overview
3
3
years of professional experience
2
2
years of post-secondary education
Work History
Physical Verification Sign-off Engineer
MediaTek Singapore
07.2021 - Current
- Spearheaded SoC verification for cutting-edge smartphone and Wi-Fi projects, adept across multiple process nodes including 22nm, 12nm, 6nm, and 4nm
- Established expert in DRC and LVS, efficiently diagnosing and solving power/ground shorts for both block and full-chip layouts
- Proficient with industry-standard EDA Tools such as ThunderView and Calibre
- Partnered with Physical Design and Packaging teams to guarantee PV standards, maintaining the integrity and dependability of end products.
Education
Masters of Science (Electronics) -
Nanyang Technological University, Singapore
07.2019 - 06.2020
Bachelors of Science (Honors) Physics - undefined
University of Delhi, India
07.2019 - 06.2020
Skills
Scripting Language: Python, C, TCL
Languages
English
Bilingual or Proficient (C2)
Spanish
Upper intermediate (B2)
Timeline
Physical Verification Sign-off Engineer
MediaTek Singapore
07.2021 - Current
Masters of Science (Electronics) -
Nanyang Technological University, Singapore
07.2019 - 06.2020
Bachelors of Science (Honors) Physics - undefined
University of Delhi, India
07.2019 - 06.2020
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